1. Field of the Invention
The present invention relates to electronic imaging. More particularly, the present invention is related to the structural design of a wafer-scale cluster image sensor chip and method of making.
2. Related Background Art
An important trend of electronic imaging with an areal image sensor chip is the increase of total imaging field size while preserving high pixel-pixel registration accuracy within the chip, ideally absent of any anomalous inter-pixel gaps. Other than a fundamental limitation imposed upon the total imaging field size by the semiconductor wafer size, another potential indirect limitation on the total imaging field size comes from a maximum allowable imaging field size (MIFS) of a wafer processing foundry fabricating the semiconductor wafer and this was already illustrated in U.S. Ser. No. 12/506,254. More specifically, the MIFS is the maximum allowable single imaging field size of a precision step-and-repeat photolithographic imaging equipment defining the specific integrated circuit pattern to be created out of the wafer. Here, a specific MIFS is characterized by a maximum allowable imaging field size MIFSX along the X-direction and a maximum allowable imaging field size MIFS along the Y-direction. Similar to U.S. Ser. No. 12/506,254 however further extended to areal imaging, the primary object of the present invention to provide an areal cluster image sensor chip for a large imaging field size exceeding the MIFS without anomalous inter-pixel gaps while avoiding the problem of low wafer imaging throughput associated with wafer stitching technology.